Secure Element

A Secure Element restricts access to protected memory and operations through a defined interface. Tamper resistance means defense against a particular attack model, not impossibility of extracting secrets. Physical analysis, fault injection and side channels are assessed together with the time, equipment and capabilities assumed for an attacker. [Trezor — Secure Elements in Trezor Safe devices] [GlobalPlatform — Secure Element Protection Profile and Extensions]

The chip may hold cryptographic keys, an auxiliary secret protecting a seed, an attempt counter or a device certificate. The claim that a private key never leaves the chip applies only to a specific architecture and key. Identify which operation happens inside the Secure Element and what remains in the main microcontroller. [Trezor — Secure Elements in Trezor Safe devices] [Tropic Square — TROPIC01 public design repository]

Trezor describes OPTIGA Trust M (V3) in Safe 3 and Safe 5. It holds an auxiliary secret that, together with the PIN, protects private keys stored on the main chip; this does not mean all Bitcoin signatures are made inside the Secure Element. Documentation also lists hardware attempt limits, authenticity checks and a randomness contribution. [Trezor — Secure Elements in Trezor Safe devices]

A certificate and device response can establish a manufacturer connection within the verification protocol's limits. They do not confirm a transaction's recipient or the harmlessness of everything shown by the host computer. Device attestation, firmware checks and user payment approval are different security steps, not one interchangeable chip property. [Trezor — Secure Elements in Trezor Safe devices] [Trezor — TROPIC01 chip vulnerability disclosure]

Common Criteria evaluates a defined target and security requirements. A component's EAL6+ does not automatically cover the entire product or every future firmware. The GlobalPlatform Protection Profile defines function and configuration scope; version 2.0 from July 2025 aligns with CC:2022. Read the specific certificate, configuration and threat model, not just the level number. [GlobalPlatform — Secure Element Protection Profile and Extensions] [Trezor — Secure Elements in Trezor Safe devices]

The TROPIC01 repository publishes RTL, application firmware and the security architecture of a chip with a RISC-V core and SPECT coprocessor. It also states that the current bootloader is not public because of IP providers' rights. Openness describes particular available parts; auditability alone proves neither absence of bugs nor conformity of every delivered unit. [Tropic Square — TROPIC01 public design repository]

Trezor disclosed Ledger Donjon's January 2026 finding: laboratory laser fault injection bypassed firmware verification on a standalone TROPIC01 and exposed its secrets. The impact description says this affected one layer of Safe 7, with other layers provided by OPTIGA and STM32U5. This is not automatically a complete wallet compromise, but must not be hidden behind an unbreakable-chip claim. [Trezor — TROPIC01 chip vulnerability disclosure]

A leaked separate seed backup bypasses device protection. Nor can the chip alone recognize a fraudulent address approved by the user. Assess recovery, display, firmware, randomness sources and vendor response alongside the exact chip model. For the cited TROPIC01 finding, the vendor explicitly describes a hardware limitation; do not assume any firmware update resolves it. [Trezor — Secure Elements in Trezor Safe devices] [Trezor — TROPIC01 chip vulnerability disclosure]